RISC-V is attracting attention from uses recently especially after acquisition of ARM by Softbank.
Specification of RISC-V is well documented. I found its ISA is very simple and suitable for high performance micro architecture; no flag is necessary for conditional branch.
I saw "Hello world" of RISC-V on JCPU within a day!. Although only user mode 32bit integer instructions are implemented, I don't see any difficulty to support further instructions.
The biggest hurdle I'm struggling is version up of LLVM. Afte LLVM-3.6, OldJIT is removed and only MCJIT is available. The MCJIT does not allow adding function to module once a module is translated. It is crucial for my use. I need to build module for each code block of target program.
The change takes time, which is not available for me ;-)
During writing a test bench of RISC-V, I found very easy-to-use elf load library ELFIO. It really is handy because header-only style and written in C++.